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All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low
Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints
on how register accesses are performed, as described in the following sections.
5.3.1.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into
the Low Energy clock domain to maintain data consistency and predictable operation. There are two
different synchronization mechanisms on the Giant Gecko, immediate synchronization, and delayed
synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and
results in an immediate update of the target registers. Delayed synchronization is used for the remaining
Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges of the
clock on the Low Energy Peripheral being accessed. Registers requiring synchronization are marked
"Asynchronous in their description header.
Note
On the Gecko series of devices, all LE peripherals are subject to delayed synchronization.
5.3.1.1.1 Delayed synchronization
After writing data to a register which value is to be synchronized into the Low Energy Peripheral using
delayed synchronization, a corresponding busy flag in the <module_name>_SYNCBUSY register (e.g.
LCD_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon
completion.
Note
Subsequent writes to the same register before the corresponding busy flag is cleared is not
supported. Write before the busy flag is cleared may result in undefined behavior.
In general the SYNCBUSY register only needs to be observed if there is a risk of multiple
write access to a register (which must be prevented). It is not required to wait until the
relevant flag in the SYNCBUSY register is cleared after writing a register. E.g can EM2 be
entered directly after writing a register.
See Figure 5.3 (p. 21) for an overview of the writing mechanism operation.
Figure 5.3. Write operation to Low Energy Peripherals
Core Clock Dom ain
Low Frequency Clock Dom ain
Core Clock
Regist er 0
Regist er 1
.
.
.
Regist er n
Freeze
Low Frequency Clock
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Low Frequency Clock
Regist er 0 Sync
Regist er 1 Sync
.
.
.
Regist er n Sync
Synchronizat ion Done
Writ e[ 0:n]
Set 0
Set 1
Set n
Syncbusy Regist er 0
Syncbusy Regist er 1
.
.
.
Syncbusy Regist er n
Clear 0
Clear 1
Clear n
5.3.1.1.2 Immediate synchronization
In contrast to the peripherals with delayed synchronization, peripherals with immediate synchronization
don't experience a delay from a value is written to it takes effect in the peripheral. They are updated
2012-04-24 - Giant Gecko Family - d0053_Rev0.96
21
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